1. Field of the Invention
This invention relates to semiconductor devices, Micro Electro Mechanical Systems (MEMS), sensors and more specifically to three dimensional (3D) three-axis accelerometers, vibration sensors and inclinometers for consumer and other applications.
2. Description of the Related Art
MEMS accelerometers are known for more than 30 years and they are widely used in different areas. Automotive air-bag applications currently represent the biggest MEMS accelerometer market.
There are only few known MEMS three-axis (or 3D) accelerometers that can measure all three components of an acceleration vector.
The market for 3D accelerometers includes hand-held devices (cell phones, PDAs, hand-held computers, gaming devices, remote controls, etc.); health and sport products (ergometers, smart shoes, patient posture indicators, pacemakers, biometric devices and systems, etc.); monitoring systems for civil objects (bridges, buildings, etc.); smart toys; virtual reality devices, and more. However, available 3D accelerometers impede market growth because of their high cost. Most of the above markets require low-cost, stable and reliable 3D accelerometers. Therefore, there is a need for a low-cost single die 3D accelerometer that possesses all the above-mentioned features.
FIG. 1 illustrates a structure of a three-axis accelerometer known from the prior art (U.S. Pat. No. 5,485,749).
Fabrication of this 3D accelerometer requires special silicon-on-insulator (SOI) material. SOI silicon wafers are standard initial material for many semiconductor devices. SOI wafers are fabricated using fusion bonding of two silicon wafers. At least one silicon wafer contains an insulator layer at the bonding interface. Therefore, two layers of silicon are electrically insulated after bonding. Thermally grown silicon dioxide is usually used as a dielectric layer at the interface of the bonded silicon wafers. After bonding, one wafer is usually thinned down to a predetermined thickness that is typically much smaller than the initial thickness of the wafer. This thin layer is used for fabrication of functional components of semiconductor devices and is called a device layer. The other wafer is typically not thinned and is called a handle wafer or handle layer.
Either one or both wafers used for SOI wafer fabrication can be micromachined before bonding. A profile is formed at the sides of the wafers that are facing each other during the bonding process. This allows making SOI wafers with buried cavities.
The 3D accelerometer die 10 shown in FIG. 1 is described in the U.S. Pat. No. 5,485,749. It is fabricated from SOI wafer with buried cavities. The thickness of the device layer 30 is much smaller than the thickness of the handle layer 28. The buried cavities 32 are located at the interface between the device and the handle layers.
The structure of the 3D accelerometer contains a frame 12, a proof mass 14 and an elastic element (suspension beams 16, 18, 20, 22) that connects the frame 12 and the proof mass 14. When acceleration is applied to the proof mass 14, it tends to move with respect to the frame causing mechanical stress in the suspension beams 16, 18, 20, and 22. Piezoresistors 24, 26 located on the suspension beams are used to generate electrical signals in response to the mechanical stress. All three components of acceleration vector can be determined by processing the signals from the piezoresistors 24, 26.
The proof mass 14 is formed by double-side etching. In the structure shown in FIG. 1, deep backside wet etching is used to etch through the handle layer 28. The device layer 30 is micromachined by etching slots 38 from the front side of the SOI wafer. These slots are connected with the cavities 36 etched from the backside of the wafer and separate the proof mass 14 and the frame 12.
The suspension beams 16, 18, 20, and 22 are formed by etching slots 38 through the device layer from the front side of the SOI wafer.
The 3D accelerometer structure described above has several disadvantages.
The state-of-the-art multi-axis accelerometers integrate both sensor elements and IC circuits for analog and digital signal conditioning and processing on the same chip. Therefore, it is desirable to minimize the area occupied by the proof mass and the suspension on the front side of the chip where the IC circuits are located.
In the die shown in FIG. 1, the area occupied by the proof mass 14 and the suspension 16, 18, 20, and 22 on the front side of the wafer is not used for any IC circuitry.
The volume and the value of the proof mass are limited by the area of elastic element and can't be increased further.
Besides that, the described three-axis accelerometer does not provide means for protection of the accelerometer structure from shock overload.